cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python (by cocotb)

Cocotb Alternatives

Similar projects and alternatives to cocotb

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better cocotb alternative or higher similarity.

Suggest an alternative to cocotb

Reviews and mentions

Posts with mentions or reviews of cocotb. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-09-21.
  • What is the relation between Python and FPGA? | 2021-09-21
    You need an actual test setup. Clone the repo, go to examples, and run make TOPLEVEL_LANG=vhdl SIM=ghdl and see what happens.
  • What is the canonical way to test and simulate Chisel gateware ? | 2021-09-15
    CocoTB (Python): I like this python test library. It easy to use, lot's of library to test i2c, uart, wishbone, ... And ... it's Python it's easy ! You can use the simulator you want and even switch between several without big problems. But it's slow simulation even with Verilator (beta) as backend.
  • Chisel/Firrtl Hardware Compiler Framework | 2021-07-05
  • Is it bad practice to use backslash line continuation?
    I had never heard of autopep8. I found this which led me to this. It seems fine.
  • Assigning values to Verilog parameters from Cocotb? | 2021-03-14
    I could see such parameters being modified in only one example from the documentation but they seemed to have assigned some fixed values in the Makefile itself and change the Makefile manually from test to test.
  • Lion: A formally verified, 5-stage pipeline RISC-V core | 2021-03-04
    After playing with some of the alternative HDLs (and even trying to make my own at one point) I've come back to just coding the design in VHDL (which I prefer over Verilog/SystemVerilog) and using cocotb ( for creating testbenches. I think in a lot of cases using VHDL generate statements can do a lot of the things these alternative HDLs are trying to do. The alternative HDLs try to shoehorn HDL semantics (everything happens in parallel) into languages that are serial and it ends up being awkward.

    Get comfortable with an HDL. Use something like cocotb to generate testbenches.

  • Can someone please explain to me the basic parts of a Cocotb testbench? | 2021-03-03
    More projects using cocotb:
  • Having troubles with installling cocotb | 2021-02-16
    You can use github with the "blame" and "history" views to see that this change comes from 2 years ago:
  • FPGA development board for beginners programmable w/ floss toolchain | 2020-12-31
    I find it interesting that C/C++ is as high as it is. Python has also had an uptick this year. I’ve seen a few people on this subreddit mention cocotb. I could see that being useful for my current project to visualize data coming from FIR filters.
  • How useful has CocoTB been for you? | 2020-12-27
    For verilator dump files, make noise here: Or maybe take a look at implementing that, it looks like it would be pretty straightforward to add a command-line option for the dump file name, and then set that in the make file. | 2020-12-27
    My only negative point is, as already mentioned, it's slower than pure HDL testbenches. I can only speak for cocotb + GHDL. When porting some testbenches to cocotb, the execution time was around four times as much, even when applying the suggested workarounds.


Basic cocotb repo stats
4 days ago

cocotb/cocotb is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.

SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives

Popular Comparisons

Find remote Python jobs at our new job board There are 7 new remote jobs listed recently.
Are you hiring? Post a new remote job listing for free.