cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python (by cocotb)

Cocotb Alternatives

Similar projects and alternatives to cocotb

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better cocotb alternative or higher similarity.

cocotb reviews and mentions

Posts with mentions or reviews of cocotb. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-07-04.
  • Designing a Low Latency 10G Ethernet Core
    2 projects | /r/FPGA | 4 Jul 2023
    The use of cocotb and pyuvm for verification
  • How is Python used in test automation in embedded systems?
    2 projects | /r/embedded | 19 Apr 2023
    For FPGA/HDL work, there's cocotb
  • Introducing CoHDL
    5 projects | /r/FPGA | 15 Apr 2023
    At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
    5 projects | /r/FPGA | 15 Apr 2023
    Regarding testbenches, they are currently not supported in CoHDL, but you can use Cocotb or any other existing test framework to check the produced VHDL representation.
  • Trying to learn and work with FPGAs
    4 projects | /r/FPGA | 12 Apr 2023
    On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
  • Error when running cocotb using cocotb-test
    2 projects | /r/FPGA | 6 Jun 2022
    The only cocotb-supported version of Verilator is 4.106 (see this). But I tried that and quickly ran into issues. I have commercial access to questa sim and the same modules and testbenches worked just fine with that.
  • Cocotb
    3 projects | /r/FPGA | 7 Nov 2021
  • How to simulate Verilog designs REALLY quickly ?
    4 projects | /r/FPGA | 7 Nov 2021
    I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?
  • What is the relation between Python and FPGA?
    2 projects | /r/FPGA | 21 Sep 2021
    You need an actual test setup. Clone the repo, go to examples, and run make TOPLEVEL_LANG=vhdl SIM=ghdl and see what happens.
  • What is the canonical way to test and simulate Chisel gateware ?
    3 projects | /r/chisel | 15 Sep 2021
    CocoTB (Python): I like this python test library. It easy to use, lot's of library to test i2c, uart, wishbone, ... And ... it's Python it's easy ! You can use the simulator you want and even switch between several without big problems. But it's slow simulation even with Verilator (beta) as backend.
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