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Top 3 Scala chip-generator Projects
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Project mention: Calyx: Intermediate Language for Hardware Accelerators | news.ycombinator.com | 2024-02-26
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
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chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Scala chip-generator discussion
Scala chip-generator related posts
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Can anyone explain simply how OpenSource the RISC-V actually is?
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Stages of prototyping a RISC-V processor on an FPGA?
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FPGA for RISC-V Processor
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Project ideas for RISC-V?
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Question: Does the 32bit version of Rocket still supports FPU
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The First Affordable RISC-V Computer Designed to Run Linux
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Is there an open source application from which to design/build a risc-v ISA processor?
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A note from our sponsor - SaaSHub
www.saashub.com | 8 Dec 2024
Index
What are some of the best open-source chip-generator projects in Scala? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | chisel | 4,014 |
| 2 | rocket-chip | 3,280 |
| 3 | chipyard | 1,675 |
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