Verilog Ethernet components for FPGA implementation (by alexforencich)

Verilog-ethernet Alternatives

Similar projects and alternatives to verilog-ethernet

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better verilog-ethernet alternative or higher similarity.

verilog-ethernet reviews and mentions

Posts with mentions or reviews of verilog-ethernet. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-05-21.
  • Using Si5324 as a clock generator on virtex-7 board
    2 projects | /r/FPGA | 21 May 2023
    For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like See for an example that targets the Si5341 specifically.
  • DE2-115 Ethernet Network Setup
    2 projects | /r/FPGA | 25 Mar 2023
    For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
  • ROS 2 Humble in AMD KR260 with Yocto
    2 projects | /r/ECE | 28 Feb 2023
    No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
  • Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
    3 projects | /r/FPGA | 28 Nov 2022
  • Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
    7 projects | /r/FPGA | 22 Aug 2022
    Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
  • 1G Ethernet Using SGMII PHY
    2 projects | /r/FPGA | 27 Jun 2022
    Decent reference design:
  • [CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
    4 projects | /r/FPGA | 4 Apr 2022
  • Ethernet on FPGA
    3 projects | /r/FPGA | 12 Dec 2021
    Alex's verilog-eth might be helpful
  • Share some github FPGA projects (bonus if they include C++, Python, or other files)
    15 projects | /r/FPGA | 14 Sep 2021
    UDP stack for operation up to 25 Gbps: . Includes example designs for a number of different boards as well as a Python-based simulation framework.
  • FPGA development live stream: 10G Ethernet on Intel Stratix 10 MX and DX
    2 projects | /r/FPGA | 6 May 2021
    For various reasons, I need to port corundum to run on Intel Stratix 10 MX and DX. As part of this process, I need to bring up both the PCIe and Ethernet interfaces on both of the cards. Also, even though both devices are Stratix 10, they use different tiles (H-tile on the MX vs. E-tile and P-tile on the DX) so the interface and capabilities are actually rather different. So, next week I'll run through the bring-up of a 10 Gbps link on both of these FPGAs by building example designs for verilog-ethernet. This will include setting up the H-tile and E-tile for operation at 10 Gbps as well as some debugging with both signaltap and the quartus "system console". If you want to learn a bit about how Intel FPGAs are put together, how 10G Ethernet works at the physical layer, and some of the techniques for debugging high speed serial links, be sure to tune in.
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