Verilog-ethernet Alternatives

Similar projects and alternatives to verilog-ethernet

• corundum

  28 1,449 9.4 Verilog verilog-ethernet VS corundum

  Open source FPGA-based NIC and platform for in-network compute

  

• satcat5

  25 386 3.8 VHDL verilog-ethernet VS satcat5

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• SpinalHDL

  8 1,506 9.8 Scala verilog-ethernet VS SpinalHDL

  Scala based HDL

  

• cocotbext-axi

  4 181 4.6 Python verilog-ethernet VS cocotbext-axi

  AXI interface modules for Cocotb

• litex

  29 2,672 9.7 C verilog-ethernet VS litex

  Build your hardware, easily!

• rohd

  8 346 8.2 Dart verilog-ethernet VS rohd

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  

• embox

  34 1,098 9.9 C verilog-ethernet VS embox

  Modular and configurable OS for embedded applications

  

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• pyxsi

  4 54 4.4 C++ verilog-ethernet VS pyxsi

  Python/C/RTL cosimulation with Xilinx's xsim simulator

• verilog-wishbone

  1 98 0.0 Python verilog-ethernet VS verilog-wishbone

  Verilog wishbone components

• xfcp

  5 51 0.0 Verilog verilog-ethernet VS xfcp

  Extensible FPGA control platform

• SBusFPGA

  5 43 5.6 Python verilog-ethernet VS SBusFPGA

  Stuff to put a FPGA in a SBus system (SPARCstation)

• liteeth

  2 190 8.9 Python verilog-ethernet VS liteeth

  Small footprint and configurable Ethernet core

• fiate

  4 7 0.0 VHDL verilog-ethernet VS fiate

  Fault Injection Automatic Test Equipment

  

• FPGA_RealTime_and_Static_Sobel_Edge_Detection

  3 34 0.0 Verilog verilog-ethernet VS FPGA_RealTime_and_Static_Sobel_Edge_Detection

  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

• BYU_PYNQ_PR_Video_Pipeline_Hardware

  2 7 0.0 VHDL verilog-ethernet VS BYU_PYNQ_PR_Video_Pipeline_Hardware

  BYU Pynq PR Video Pipeline Hardware

  

• BYU_PYNQ_PR_Video_Pipeline

  2 14 0.0 Jupyter Notebook verilog-ethernet VS BYU_PYNQ_PR_Video_Pipeline

  The Demo that was presented at FCCM.

  

• WARP_Core

  2 7 0.0 VHDL verilog-ethernet VS WARP_Core

  Wilson AXI RISCV Processor Core

• RedPitaya_Acquisition

  1 26 2.6 VHDL verilog-ethernet VS RedPitaya_Acquisition

  Transform the Red Pitaya in an acquisition card

• gateware

  1 25 5.7 Verilog verilog-ethernet VS gateware

  IP submodules, formatted for easier CI integration

  

• axis_udp

  1 24 0.0 Verilog verilog-ethernet VS axis_udp

  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

• SaaSHub

  www.saashub.com sponsored

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives