Verilog-ethernet Alternatives

Similar projects and alternatives to verilog-ethernet

• corundum

  3 1,349 0.0 Verilog verilog-ethernet VS corundum

  Open source FPGA-based NIC and platform for in-network compute

  

• satcat5

  4 239 0.0 VHDL verilog-ethernet VS satcat5

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

• InfluxDB

  www.influxdata.com

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• SpinalHDL

  1 1,410 9.3 Scala verilog-ethernet VS SpinalHDL

  Scala based HDL

  

• litex

  - 2,474 0.0 C verilog-ethernet VS litex

  Build your hardware, easily!

• cocotbext-axi

  1 162 0.0 Python verilog-ethernet VS cocotbext-axi

  AXI interface modules for Cocotb

• embox

  - 1,030 9.7 C verilog-ethernet VS embox

  Modular and configurable OS for embedded applications

  

• verilog-wishbone

  1 92 0.0 Python verilog-ethernet VS verilog-wishbone

  Verilog wishbone components

• Onboard AI

  getonboard.dev

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• liteeth

  1 182 0.0 Python verilog-ethernet VS liteeth

  Small footprint and configurable Ethernet core

• pyxsi

  1 44 4.1 C++ verilog-ethernet VS pyxsi

  Python/C/RTL cosimulation with Xilinx's xsim simulator

• BYU_PYNQ_PR_Video_Pipeline_Hardware

  1 6 0.0 VHDL verilog-ethernet VS BYU_PYNQ_PR_Video_Pipeline_Hardware

  BYU Pynq PR Video Pipeline Hardware

  

• rohd

  1 297 0.0 Dart verilog-ethernet VS rohd

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  

• xfcp

  1 50 0.0 Verilog verilog-ethernet VS xfcp

  Extensible FPGA control platform

• SBusFPGA

  1 40 0.0 Python verilog-ethernet VS SBusFPGA

  Stuff to put a FPGA in a SBus system (SPARCstation)

• FPGA_RealTime_and_Static_Sobel_Edge_Detection

  1 33 0.0 Verilog verilog-ethernet VS FPGA_RealTime_and_Static_Sobel_Edge_Detection

  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

• gateware

  1 26 0.0 Verilog verilog-ethernet VS gateware

  IP submodules, formatted for easier CI integration

  

• RedPitaya_Acquisition

  1 25 2.7 VHDL verilog-ethernet VS RedPitaya_Acquisition

  Transform the Red Pitaya in an acquisition card

• axis_udp

  1 16 0.0 Verilog verilog-ethernet VS axis_udp

  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

• BYU_PYNQ_PR_Video_Pipeline

  1 14 0.0 Jupyter Notebook verilog-ethernet VS BYU_PYNQ_PR_Video_Pipeline

  The Demo that was presented at FCCM.

  

• fiate

  1 6 0.0 VHDL verilog-ethernet VS fiate

  Fault Injection Automatic Test Equipment

  

• WARP_Core

  1 6 0.0 VHDL verilog-ethernet VS WARP_Core

  Wilson AXI RISCV Processor Core

• SaaSHub

  www.saashub.com

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