Litedram Alternatives

Similar projects and alternatives to litedram

litex

29 2,672 9.7 C litedram VS litex

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VexRiscv

21 2,244 7.6 Assembly litedram VS VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
WorkOS

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cva6

10 2,067 9.7 Assembly litedram VS cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SpinalHDL

8 1,506 9.8 Scala litedram VS SpinalHDL

Scala based HDL
openwifi

10 3,547 7.6 C litedram VS openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
litepcie

2 432 8.7 Python litedram VS litepcie

Small footprint and configurable PCIe core
SaxonSoc

1 140 4.8 Scala litedram VS SaxonSoc

SoC based on VexRiscv and ICE40 UP5K
InfluxDB

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hdcp

3 35 0.0 C++ litedram VS hdcp
OpenSERDES

1 115 10.0 Verilog litedram VS OpenSERDES

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better litedram alternative or higher similarity.

Suggest an alternative to litedram

litedram reviews and mentions

Posts with mentions or reviews of litedram. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-14.

How Much Would It Cost For A Truly Open Source RISC-V SOC?
5 projects | /r/RISCV | 14 Jan 2023

I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.
I am trying to avoid AXI Bus for DDR3 access on Arty A7
1 project | /r/FPGA | 17 Aug 2022

Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.
LiteDRAM – A fully open-source memory controller targeting LPDDR4/5 for FPGA
1 project | news.ycombinator.com | 29 Apr 2022
Suggest advance project ideas
3 projects | /r/FPGA | 3 Sep 2021

You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
How many more years until we have a completely open source RISC-V SOC?
6 projects | /r/RISCV | 26 May 2021

So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.
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www.influxdata.com | 18 Apr 2024

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