SpinalHDL VS verilog-ethernet

I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

I really like what Zig and C++ are doing with `const`.

https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

Have you looked at Spinal?

https://github.com/SpinalHDL/SpinalHDL

https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

[1] https://github.com/ucb-bar/chipyard

[2] https://github.com/SpinalHDL/SpinalHDL

[3] https://github.com/B-Lang-org/bsc

I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.

Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.

A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.

Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.

For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.

For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.

No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.

So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.

I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.

I was studying Alex Forencich's FCS verilog and noticed the following always block:

This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet