verilog-ethernet VS cocotbext-axi

Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.

For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.

For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.

No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.

So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.

I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.

I was studying Alex Forencich's FCS verilog and noticed the following always block:

This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet

0.00ns INFO ..b.dma_wrapper.m_axi_s2mm AXI slave model (write) 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm cocotbext-axi version 0.1.24 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Copyright (c) 2021 Alex Forencich 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm https://github.com/alexforencich/cocotbext-axi 0.00ns DEBUG gpi m_axi_s2mm_awvalid has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_awprot has 3 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_wvalid has 1 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_bvalid has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_bready has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_bresp has 2 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_awaddr has 32 elements

I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.

This is where you can use a BFM (bus functional model). Basically, you can connect your design to a simulation model of the RAM. I wrote some cocotb extensions for doing stuff like this in cocotb, you can give that a try, assuming your code works with a simulator that's compatible with cocotb: https://github.com/alexforencich/cocotbext-axi

The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.