[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​

• verilog-ethernet

  32 1,901 8.8 Verilog

  Verilog Ethernet components for FPGA implementation

• rohd

  8 347 8.2 Dart

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  

You might be interested in checking out ROHD as well: https://github.com/intel/rohd

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• pyxsi

  4 54 4.4 C++

  Python/C/RTL cosimulation with Xilinx's xsim simulator

The sketch here is a little stale but shows the general idea.

• cocotbext-axi

  4 181 4.6 Python

  AXI interface modules for Cocotb

I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.

Suggest a related project