[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​

• verilog-ethernet

  18 1,503 0.0 Verilog

  Verilog Ethernet components for FPGA implementation

• rohd

  3 261 4.2 Dart

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language. ROHD enables you to build and traverse a graph of connectivity between module objects using unrestricted software.

  

  You might be interested in checking out ROHD as well: https://github.com/intel/rohd

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• pyxsi

  2 31 3.4 C++

  Python/C/RTL cosimulation with Xilinx's xsim simulator

  The sketch here is a little stale but shows the general idea.

• cocotbext-axi

  0 126 0.0 Python

  AXI interface modules for Cocotb

  I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.

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