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Verilog Ethernet components for FPGA implementation
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language. ROHD enables you to build and traverse a graph of connectivity between module objects using unrestricted software.
You might be interested in checking out ROHD as well: https://github.com/intel/rohd
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Python/C/RTL cosimulation with Xilinx's xsim simulator
The sketch here is a little stale but shows the general idea.
AXI interface modules for Cocotb
I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.
Building a HDL (Kind of)
1 project | /r/FPGA | 2 Dec 2022
2 projects | /r/neoliberal | 1 Oct 2022
Choice of Python HDL library
10 projects | /r/FPGA | 25 Jul 2022
VRoom A high end RISC-V implementation
4 projects | news.ycombinator.com | 21 Mar 2022
UCLA Adopts PyGears, an Open Source Framework for FPGA AI Design
1 project | /r/FPGA | 16 Mar 2022