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hVHDL_example_project
An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
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CodeRabbit
CodeRabbit: AI Code Reviews for Developers. Revolutionize your code reviews with AI. CodeRabbit offers PR summaries, code walkthroughs, 1-click suggestions, and AST-based analysis. Boost productivity and code quality across all major languages with each PR.
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I also happen to really believe in RTL design using high-level languages to enable software design techniques such as object orientation. My master's thesis was written entirely in Migen and I think it served me extremely well.
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While I think Migen is a really nice library, it's also a pretty dead project, since the main people behind it moved over to Amaranth. It has one large upside in the fact Litex still uses it as the backend and they seem on the fence between moving over to Amaranth or rolling their own HDL library. For me Litex feels very important, but at the same time, my focus is on compute kernels and not some complicated NOCs.
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MyHDL
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pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
PyMTL
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The file has 86 lines, but this functionality could be implemented with just 10 lines of code by using a procedure call to create_first_order_filter which can is defined here https://github.com/hVHDL/hVHDL_floating_point/blob/main/float_first_order_filter/float_first_order_filter_pkg.vhd
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rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Check out ROHD: https://github.com/intel/rohd
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
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hVHDL_fixed_point
VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
How this works in practice can be seen for example in a rom module. https://github.com/hVHDL/hVHDL_math_library/blob/main/sincos/lut_sine_pkg.vhd