- iCEstick LPC TPM Sniffer
- OpenROAD
- Lichee Pi 4A: Serious RISC-V Desktop Computing [video]
- Fixing the TPM: Hardware Security Modules Done Right
- Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
- Nuked-MD-FPGA -- cycle-accurate Sega Genesis/MD hardware implementation based on reverse-engineering console's chips
- Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
- Ultraembedded RISCV Module
- A Single-Cycle 64-Bit RISC-V Register File
- Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
- Graphics-gremlin – open-source retro ISA video card
- SDRAM controller for the Tang Nano 20K
- Commodore 64 VIC-II 6567/6569 Replacement Project
- Do you think the Tang Nano 20k has much chance of emulating an IBM PC/XT?
- Best way to downgrade a core?
- SNES + FXPAK pro s-video audio issues (cutting in and out / lowering of volume)
- MVS to AES adapters: how do they work?
- Looking for help getting started with TinyFPGA
- Digital interface for analog channel
- testbenches with Xilinx IP ?
- antongale/arcade-taitosj 0.1.0 Core Released for Analogue Pocket
- Ser programador científico en chile
- Developing APB2 Peripheral for Gowin Tangnano 4K FPGA Dev Board: Sharing My Journey
- Recommended replacement PLA options and advice?
- FPGA based MIT CADR lisp machine - rewritten in modern verilog
- SERV: A bit-serial RISC-V core
- Need help with designing a basic RISC V processor?
- asynchronous FIFO code not working
- Designing FPGA SERDES lab experiment
- Has anyone ever made a z80 out of 7400 series parts?
- Ethernet communication in FPGA
- ESdUDO The cheapest replacement for a 8bit computer.
- Configuring FTDI chip as synchronous fifo
- SERV – open-source Tiny SErial RISC-V CPU
- Using the OSS PsramController with both dies
- C++ Verification Testbench Best-Practice Resources?
- Virtual FPGA
- (Help)Issue with Battle Bakraid
- Gyurco porting Furrtek’s Neogeo to MIST and other FPGAs
- Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS
- ARM’s Cortex A53: Tiny but Important
- Половина российских компаний лишились иностранного софта
- Quartus Tcl Build Script
- Final Year Project on RISC-V?
- Using Si5324 as a clock generator on virtex-7 board
- TCP checksum computation
- Recreating RP2040 PIO Interface in an FPGA
- Recreating RP2040 PIO Interface in an FPGA
- awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi
- SPI PROTOCOL in FPGA