Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro (by eugene-tarassov)

Vivado-risc-v Alternatives

Similar projects and alternatives to vivado-risc-v

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better vivado-risc-v alternative or higher similarity.

vivado-risc-v reviews and mentions

Posts with mentions or reviews of vivado-risc-v. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.
  • Recommendations for RISC-V on FPGA
    7 projects | /r/FPGA | 8 Mar 2023
    Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
  • How can I learn about RISC-V and use case? I want to do a project for begginers
    2 projects | /r/FPGA | 5 Feb 2023
  • Open-source RISC-V CPU projects for contribution
    8 projects | /r/RISCV | 28 Jan 2023
    For Xilinx FPGAs :
  • Running Hello World on a bare-metal RISC-V FPGA
    3 projects | /r/RISCV | 10 Jan 2022
    But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.
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