SaxonSoc

SoC based on VexRiscv and ICE40 UP5K (by SpinalHDL)

SaxonSoc Alternatives

Similar projects and alternatives to SaxonSoc based on common topics and language

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better SaxonSoc alternative or higher similarity.

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Reviews and mentions

Posts with mentions or reviews of SaxonSoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-05-26.
  • How many more years until we have a completely open source RISC-V SOC?
    reddit.com/r/RISCV | 2021-05-26
    Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.

Stats

Basic SaxonSoc repo stats
1
93
8.6
8 days ago

SpinalHDL/SaxonSoc is an open source project licensed under MIT License which is an OSI approved license.

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