Python Frontend For VHDL And Verilog
SonicBOOM: The Berkeley Out-of-Order Machine
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
Collect and Analyze Billions of Data Points in Real Time. Manage all types of time series data in a single, purpose-built database. Run at any scale in any environment in the cloud, on-premises, or at the edge.
Cascade: CPU Fuzzing via Intricate Program Generation
3 projects | news.ycombinator.com | 23 Oct 2023
In your opinion, what is the most advanced open source softcore processor?
2 projects | /r/FPGA | 28 May 2023
Semidynamics Unveils First Customizable RISC-V Cores for End Users
1 project | /r/RISCV | 21 Apr 2023
The Surprising Subtleties of Zeroing a Register
3 projects | news.ycombinator.com | 4 Nov 2021
Fence instruction implementation in BOOM
1 project | /r/RISCV | 18 Mar 2021