Cascade: CPU Fuzzing via Intricate Program Generation

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  • sandsifter

    The x86 processor fuzzer

  • Scout Monitoring

    Free Django app performance insights with Scout Monitoring. Get Scout setup in minutes, and let us sweat the small stuff. A couple lines in settings.py is all you need to start monitoring your apps. Sign up for our free tier today.

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  • sail-riscv

    Sail RISC-V model

  • the retired instruction counters when written by software.

    Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256

  • riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

  • Looks like from Appendix D that only 2 bugs were found in BOOM:

    > 1. Inaccurate instruction count when minstret is written by software

    I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.

    > 2. Static rounding is ignored for fdiv.s and fsqrt.s

    A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.

    Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files

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