Debugging a timing loop

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  • wd65c02

    Cycle accurate FPGA implementation of various 6502 CPU variants

    • I have a design (available here) that has loops in the timing report after implementation. The problem is that I cannot seem to trace the nets I'm seeing in the report to my code, and those I did manage to trace seem to be routed through non-blocking assignments. I'm missing something, but I'm not sure what.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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