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Verilog soft-core Projects
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For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
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NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
The latest post mention was on 2022-10-20.
Verilog soft-core related posts
- SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
- Xilinx FIFO generator for skid buffer?
- Five legally free FPGA books (plus one about Machine Learning)
- What make xilinx fpga runs soft core cpu faster than lattice
- OS AXI4 Crossbar with good performance
- looking for 16 bit RISC ISA to implement on cyclon IV FPGA
- Risc-v with minimum number of gates
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A note from our sponsor - SonarLint
www.sonarlint.org | 28 Mar 2023
Index
| Project | Stars | |
|---|---|---|
| 1 | zipcpu | 1,008 |
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