Risc-v with minimum number of gates

This page summarizes the projects mentioned and recommended in the original post on reddit.com/r/FPGA
#risc-v #soft-core #Vhdl #Hardware #Fpga

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  • serv

    SERV - The SErial RISC-V CPU

  • neorv32

    🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    How about https://github.com/stnolting/neorv32 ? It is not as small as SERV (as it is not a bit-serial architecture) but still pretty small and highly configurable.

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  • panologic

    PanoLogic Zero Client G1 reverse engineering info

    That's the approach I use in all my hobby projects. Do I really need that I2C controller? Of course not, I just bitbang it on a VexRiscv CPU...

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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