OS AXI4 Crossbar with good performance

• verilog-axi

  9 1,252 3.0 Verilog

  Verilog AXI components for FPGA implementation

does anybody knows some sort of AXI4 Crossbar or maybe even an Interconnect with good performance in terms of latency? If I have something like the following scenario, the idea is that M1 txns must have very low access latency in the sense of making the CPU capable of processing at least one instruction per cc. For M2 it's fine to take more time, but what I'm observing is that with this solution for instance, I cannot achieve constant fetching from the CPU, there's always a 1 cc delay between req/resp what hits bad my IPC. Also, S1 cannot be tightly coupled to the CPU because sometimes M2 might require to also fetch from IRAM/ROM. Is it better to switch to another protocol to achieve such good performance latency? if so, what open source available solution can have interesting perf. num, wishbone / AHB?

• wb2axip

  51 431 3.1 Verilog

  Bus bridges and other odds and ends

I know of three Open Source AXI crossbars. There's my own, Bluespec has one, and so does the PULP platform as I recall.

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• zipcpu

  13 1,188 6.3 Verilog

  A small, light weight, RISC CPU soft core

If you are looking for an AXI4 cache implementation, the ZipCPU currently supports two (I+D) that you might be able to gain some insights from. There's the AXI instruction cache implementation, and an AXI4 data cache implementation. They are both one way caches. Both were featured in an article on performance measurement last year. The data cache implementation doesn't support exclusive access yet--that's still on my to-do list. You can find these caches demonstrated in my AXI DMA check repo, if you'd like to try them out.

• axidmacheck

  2 8 0.0 Verilog

  AXI DMA Check: A utility to measure DMA speeds in simulation

If you are looking for an AXI4 cache implementation, the ZipCPU currently supports two (I+D) that you might be able to gain some insights from. There's the AXI instruction cache implementation, and an AXI4 data cache implementation. They are both one way caches. Both were featured in an article on performance measurement last year. The data cache implementation doesn't support exclusive access yet--that's still on my to-do list. You can find these caches demonstrated in my AXI DMA check repo, if you'd like to try them out.

Suggest a related project