Verilog Vhdl

Open-source Verilog projects categorized as Vhdl

Top 3 Verilog Vhdl Projects

  • microwatt

    A tiny Open POWER ISA softcore written in VHDL 2008

  • Project mention: Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008 | /r/patient_hackernews | 2023-10-23
  • riscv_vhdl

    Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

    WorkOS logo
  • spam-1

    Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog Vhdl related posts

Index

What are some of the best open-source Vhdl projects in Verilog? This list will help you:

Project Stars
1 microwatt 643
2 riscv_vhdl 578
3 spam-1 60

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