rp32
cheshire
| rp32 | cheshire | |
|---|---|---|
| 3 | 1 | |
| 8 | 107 | |
| - | 8.6% | |
| 5.9 | 7.6 | |
| 8 months ago | 1 day ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
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rp32
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How to design a more elegant and simple instraction decoder
Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv
- Mapping compressed 'C' instructions to their 32b counterparts.
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Is a single cycle CPU of any use besides learning?
I am writing a RISC-V core with a strict IPC=1 (instructions per cycle). One piece is still in my mind, but the CPU is already passing instruction set tests.https://github.com/jeras/rp32The code was not properly synthesized yet, and there is almost no documentation, if you wish to use anything, but do not know how to, you can ask for help as a GitHub issue. But I do not know how much time I will have to answer.
cheshire
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Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
What are some alternatives?
riscv-formal - RISC-V Formal Verification Framework
hdmi - Send video/audio over HDMI on an FPGA
friscv - RISCV CPU implementation in SystemVerilog
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Cores-VeeR-EH1 - VeeR EH1 core
libsv - An open source, parameterized SystemVerilog digital hardware IP library
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
simple-riscv - A simple three-stage RISC-V CPU
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux