cheshire
friscv
cheshire | friscv | |
---|---|---|
1 | 1 | |
107 | 15 | |
10.3% | - | |
7.6 | 7.7 | |
3 days ago | 14 days ago | |
SystemVerilog | Coq | |
GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cheshire
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Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
friscv
What are some alternatives?
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darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
libsv - An open source, parameterized SystemVerilog digital hardware IP library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cores-VeeR-EH1 - VeeR EH1 core
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform