friscv
scr1
| friscv | scr1 | |
|---|---|---|
| 1 | 2 | |
| 17 | 848 | |
| - | 2.9% | |
| 4.7 | 3.6 | |
| 7 days ago | 19 days ago | |
| SystemVerilog | SystemVerilog | |
| MIT License | GNU General Public License v3.0 or later |
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friscv
scr1
-
Looking for a suitable open-source RISC-V for an embedded project
Would this be suitable? https://github.com/syntacore/scr1 I haven't used it, but I saw it in Riscduino project which continues to appear in Open MPWs.
- Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv-simple-sv - A simple RISC V core for teaching
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Cores-VeeR-EL2 - VeeR EL2 Core
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
clic - RISC-V fast interrupt controller
fpga_riscv_cpu - fpga verilog risc-v rv32i cpu
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation