friscv VS scr1

Compare friscv vs scr1 and see what are their differences.

friscv

RISCV CPU implementation in SystemVerilog (by dpretet)
riscv-cpu Riscv Rv32i Verilog Systemverilog Fpga Asic risc-v Assembler fpga-soc asic-design Axi4 axi4-protocol crossbar
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scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog (by syntacore)
Riscv risc-v Rtl Verilog Rv32i rv32e rv32imc rv32emc IP Core
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friscv scr1
1 2
14 768
- 2.3%
8.4 3.3
2 months ago 8 days ago
Coq SystemVerilog
MIT License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

friscv

Posts with mentions or reviews of friscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

scr1

Posts with mentions or reviews of scr1. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-07-04.

What are some alternatives?

When comparing friscv and scr1 you can also consider the following projects:

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

riscv-simple-sv - A simple RISC V core for teaching

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

clic - RISC-V fast interrupt controller

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Cores-VeeR-EL2 - VeeR EL2 Core

Cores-VeeR-EH1 - VeeR EH1 core

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

friscv vs darkriscv scr1 vs riscv-simple-sv friscv vs ravenoc scr1 vs FPGA-Video-Processing friscv vs cheshire scr1 vs clic friscv vs rp32 scr1 vs VexRiscv friscv vs cv32e40p scr1 vs Cores-VeeR-EL2 friscv vs Cores-VeeR-EH1 scr1 vs ibex