SystemVerilog Riscv

Open-source SystemVerilog projects categorized as Riscv

Top 8 SystemVerilog Riscv Projects

  • cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  • Cores-VeeR-EH1

    VeeR EH1 core

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • Cores-VeeR-EL2

    VeeR EL2 Core

  • riscv-simple-sv

    A simple RISC V core for teaching

  • cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

    Project mention: Cpu project | /r/RISCV | 2023-05-08

    If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here

  • risc-v-single-cycle

    A Single Cycle Risc-V 32 bit CPU

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  • rp32

    RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

    Project mention: How to design a more elegant and simple instraction decoder | /r/RISCV | 2023-05-24

    Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-05-24.

SystemVerilog Riscv related posts

Index

What are some of the best open-source Riscv projects in SystemVerilog? This list will help you:

Project Stars
1 cv32e40p 861
2 Cores-VeeR-EH1 765
3 scr1 763
4 Cores-VeeR-EL2 218
5 riscv-simple-sv 145
6 cheshire 96
7 risc-v-single-cycle 16
8 rp32 8
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