Coq Verilog

Open-source Coq projects categorized as Verilog
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Topics: #Asic #Fpga #risc-v #Verification #C
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Coq Verilog Projects

  • vericert

    A formally verified high-level synthesis tool based on CompCert and written in Coq.

    Project mention: There's an ongoing effort to rewrite Principia Mathematica using Coq | reddit.com/r/math | 2021-12-03

    There are ongoing research projects about that, you may want to have a look at Kôika (https://github.com/mit-plv/koika), Kami (https://github.com/mit-plv/kami), Lutsig (https://github.com/CakeML/hardware) and silveroak (https://github.com/project-oak/silveroak). Closer to HLS there is also Vericert (https://github.com/ymherklotz/vericert). There may be other research project I am unaware of, feel free to add them in a reply, I am interested in it.

  • friscv

    RISCV CPU implementation in SystemVerilog

  • InfluxDB

    Build time-series-based applications quickly and at scale.. InfluxDB is the Time Series Data Platform where developers build real-time applications for analytics, IoT and cloud-native services in less time with less code.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-12-03.

Coq Verilog related posts

Index

Project Stars
1 vericert 64
2 friscv 11

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