cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster. (by pulp-platform)
| cheshire | pulpissimo | |
|---|---|---|
| 1 | 2 | |
| 107 | 332 | |
| 10.3% | 0.0% | |
| 7.6 | 10.0 | |
| 3 days ago | about 1 year ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cheshire
Posts with mentions or reviews of cheshire.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-08.
-
Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
pulpissimo
Posts with mentions or reviews of pulpissimo.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-08.
- building pulpissimo
-
Cpu project
with the microcontroller Pulpissimo here.
What are some alternatives?
When comparing cheshire and pulpissimo you can also consider the following projects:
hdmi - Send video/audio over HDMI on an FPGA
friscv - RISCV CPU implementation in SystemVerilog
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
libsv - An open source, parameterized SystemVerilog digital hardware IP library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
ApogeoRV - A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Arithmetic-Circuits - This repository contains different modules which execute arithmetic operations.