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Top 21 C Riscv Projects
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Unicorn Engine
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
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capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core (by pulp-platform)
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SaaSHub
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Project mention: Unicorn: Lightweight multi-platform, multi-architecture CPU emulator framework | news.ycombinator.com | 2023-11-19
Project mention: Rise: Accelerate the Development of Open Source Software for RISC-V | news.ycombinator.com | 2023-05-31Maybe then they can help us with the Capstone[1][2] disassembly engine auto-sync (automatic synchronization from the LLVM TableGen files) effort[3]. ARMv7, ARMv8/9, PowerPC are nearly finished, and MIPS in in near-term plans. Nobody stepped in for RISC-V yet.
[1] http://www.capstone-engine.org/
[2] https://github.com/capstone-engine/capstone
[3] https://github.com/capstone-engine/capstone/issues/2015
Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
Project mention: A self-hosting and educational C optimizing compiler | news.ycombinator.com | 2024-01-07Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...
Project mention: x86 vs ARM; Vector and Matrix Extensions; How do they compare? | /r/hardware | 2023-12-09yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
Since you're clearly knowledgable ...
What's your take on http://cheribsd.org (and CHERI as a concept overall)?
Project mention: Star64 JH7110 RISC-V SBC: Experiments with OpenSBI (Supervisor Binary Interface) | news.ycombinator.com | 2023-10-28Thanks! The JH7110 Display Controller is super complex, it might take a while to get it working with NuttX. Right now I'm building the I2C Driver for JH7110, which is needed to power up the PMIC for HDMI Output:
https://github.com/lupyuen/nuttx-star64#power-up-the-i2c-con...
Hi, I'm a first year college student interested in embedded systems. Some projects 1 2 I have been working on. My questions are:
C Riscv related posts
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
- Ara2: RVV 1.0 Compliant Open-Source Processor
- A repository that tracks upstream but allows separate tracking.
- I got my Sipeed M1S Dock (BL808) yesterday, but I don’t see a macos toolchain for the C SDK. Am I missing something?
- RVVM – The RISC-V Virtual Machine
- RVVM – The RISC-V Virtual Machine
- RVVM – The RISC-V Virtual Machine
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Index
What are some of the best open-source Riscv projects in C? This list will help you:
Project | Stars | |
---|---|---|
1 | Unicorn Engine | 7,126 |
2 | capstone | 7,025 |
3 | neorv32 | 1,415 |
4 | chipyard | 1,411 |
5 | shecc | 1,038 |
6 | RVVM | 807 |
7 | FastLZ | 390 |
8 | ara | 304 |
9 | esp | 295 |
10 | freedom-u-sdk | 264 |
11 | cheribsd | 151 |
12 | riscv_em | 125 |
13 | nuclei-sdk | 108 |
14 | simd_utils | 79 |
15 | OpenPicoRTOS | 39 |
16 | qemu-pinning | 37 |
17 | nuttx-star64 | 23 |
18 | taurus | 9 |
19 | ch32v307-gnumake | 7 |
20 | ulisp-bl602 | 4 |
21 | ch32v00 | 0 |
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