C Riscv

Open-source C projects categorized as Riscv

Top 21 C Riscv Projects

  • Unicorn Engine

    Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

  • Project mention: Unicorn: Lightweight multi-platform, multi-architecture CPU emulator framework | news.ycombinator.com | 2023-11-19
  • capstone

    Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

  • Project mention: Rise: Accelerate the Development of Open Source Software for RISC-V | news.ycombinator.com | 2023-05-31

    Maybe then they can help us with the Capstone[1][2] disassembly engine auto-sync (automatic synchronization from the LLVM TableGen files) effort[3]. ARMv7, ARMv8/9, PowerPC are nearly finished, and MIPS in in near-term plans. Nobody stepped in for RISC-V yet.

    [1] http://www.capstone-engine.org/

    [2] https://github.com/capstone-engine/capstone

    [3] https://github.com/capstone-engine/capstone/issues/2015

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  • Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24
  • chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  • Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

    It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

    Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

    Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

    [0]: https://github.com/ucb-bar/chipyard

    [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

  • shecc

    A self-hosting and educational C optimizing compiler

  • Project mention: A self-hosting and educational C optimizing compiler | news.ycombinator.com | 2024-01-07

    Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...

  • RVVM

    The RISC-V Virtual Machine

  • FastLZ

    Small & portable byte-aligned LZ77 compression (by ariya)

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • ara

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core (by pulp-platform)

  • Project mention: x86 vs ARM; Vector and Matrix Extensions; How do they compare? | /r/hardware | 2023-12-09

    yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future

  • esp

    Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

  • freedom-u-sdk

    Freedom U Software Development Kit (FUSDK)

  • cheribsd

    FreeBSD adapted for CHERI-RISC-V and Arm Morello.

  • Project mention: OpenBSD 7.5 Released | news.ycombinator.com | 2024-04-05

    Since you're clearly knowledgable ...

    What's your take on http://cheribsd.org (and CHERI as a concept overall)?

  • riscv_em

    Simple risc-v emulator, able to run linux, written in C.

  • nuclei-sdk

    Nuclei RISC-V Software Development Kit

  • simd_utils

    A header only library implementing common mathematical functions using SIMD intrinsics

  • OpenPicoRTOS

    Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

  • Project mention: Share your open source work | /r/embeddedconsulting | 2023-05-23
  • qemu-pinning

    My QEMU fork with pinning (affinity) support and a few tweaks.

  • nuttx-star64

    Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)

  • Project mention: Star64 JH7110 RISC-V SBC: Experiments with OpenSBI (Supervisor Binary Interface) | news.ycombinator.com | 2023-10-28

    Thanks! The JH7110 Display Controller is super complex, it might take a while to get it working with NuttX. Right now I'm building the I2C Driver for JH7110, which is needed to power up the PMIC for HDMI Output:

    https://github.com/lupyuen/nuttx-star64#power-up-the-i2c-con...

  • taurus

    SDK for CDAC Vega Processors (by rnayabed)

  • Project mention: Embedded Systems Projects | /r/developersIndia | 2023-05-30

    Hi, I'm a first year college student interested in embedded systems. Some projects 1 2 I have been working on. My questions are:

  • ch32v307-gnumake

    Makefile project for ch32v307

  • ulisp-bl602

    A version of the Lisp programming language for RISC-V BL602 Boards

  • ch32v00

    Unofficial snap for ch32v00* chipset development tools

  • Project mention: ch32v00x snap | /r/RISCV | 2023-07-12
  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

C Riscv related posts

Index

What are some of the best open-source Riscv projects in C? This list will help you:

Project Stars
1 Unicorn Engine 7,126
2 capstone 7,025
3 neorv32 1,415
4 chipyard 1,411
5 shecc 1,038
6 RVVM 807
7 FastLZ 390
8 ara 304
9 esp 295
10 freedom-u-sdk 264
11 cheribsd 151
12 riscv_em 125
13 nuclei-sdk 108
14 simd_utils 79
15 OpenPicoRTOS 39
16 qemu-pinning 37
17 nuttx-star64 23
18 taurus 9
19 ch32v307-gnumake 7
20 ulisp-bl602 4
21 ch32v00 0

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