neorv32 VS linux-on-litex-vexriscv

Compare neorv32 vs linux-on-litex-vexriscv and see what are their differences.

neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
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neorv32 linux-on-litex-vexriscv
77 13
1,415 535
- 2.8%
9.9 5.4
6 days ago 19 days ago
C Python
BSD 3-clause "New" or "Revised" License BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

neorv32

Posts with mentions or reviews of neorv32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.

linux-on-litex-vexriscv

Posts with mentions or reviews of linux-on-litex-vexriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-23.
  • Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
    4 projects | /r/RISCV | 23 Oct 2023
    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
  • Education board tips
    1 project | /r/RISCV | 14 Jun 2023
    Hello, we are planning to rebuild a computer architectures course at uni and the idea is to teach the basics using the riscv architecture. We are looking for an affordable development board that could be used to demonstrate both bare-metal programming as well as interfacing hardware via mmap from OS to build up the experience with accessing the registers directly, and then introducing virtual memory, memory hierarchy, etc. So far it seems like a best option to utilize some compatible FPGA development board and the litex ( https://github.com/litex-hub/linux-on-litex-vexriscv ) project to achieve the afforementioned. Would you have any comment on that or perhaps some other recommendation for an affordable development board? Thanks for any tips.
  • RISC-V Business: Testing StarFive's VisionFive 2 SBC
    3 projects | news.ycombinator.com | 3 Mar 2023
    The repo below has support for building a 32bit RISC-V CPU for de10nano. It also includes information about booting Linux.

    https://github.com/litex-hub/linux-on-litex-vexriscv

    The CPU will likely have a clock speed around 100Mhz, far slower than the 1.5Ghz 64bit cores on the VisionFive 2 or Pi4. The FPGA might still be useful if you want to customize the CPU or integrate other custom hardware.

  • Linux on LiteX
    1 project | news.ycombinator.com | 30 Jan 2023
  • Building RISCV that can eventually run Linux OS
    1 project | /r/RISCV | 7 Sep 2022
  • CosmicStrand: The discovery of a sophisticated UEFI firmware rootkit
    2 projects | news.ycombinator.com | 26 Jul 2022
    You can run linux even on an entirely open source from hardware to software toolchain: https://github.com/litex-hub/linux-on-litex-vexriscv
  • FPGA
    1 project | /r/RISCV | 12 Mar 2022
    On the other hand, if you really want a budget FPGA board under 100 USD that can implement a Linux-capable RISC-V SoC, you will need to implement a simple 32-bit one but indeed possible. See https://github.com/litex-hub/linux-on-litex-vexriscv for instance. You will get additional frequencies (still an order of 100 MHz though), I/O ports and such if you can spend 200 to 300 USD.
  • Best fpga for making multicore linux-capable SoC?
    2 projects | /r/FPGA | 7 Mar 2022
    An Artix 7 100k (like in the 'big' Arty A7 board) will comfortably fit 4 VexRiscv @ 100 MHz in a Litex SoC with all the bells and whistles; you can already fit a SoC with 2 Vex in the smaller 35k. Running Linux on that is very easy.
  • Is it possible to build a RISCV Core on FPGA which runs Linux on top of it?
    3 projects | /r/RISCV | 26 Feb 2022
  • Why has the barrier to entry for hardware design in general reduced so slowly?
    1 project | /r/FPGA | 27 Sep 2021
    Accessibility has improved significantly over the last few years. You can now buy any of the Lattice iCE40 or ECP5 boards from this page and use the yosys open-source workflow to upload real designs to the cores, including soft cores capable of running real, unmodified Linux. These tools are actively developed and are used by the open-source FPGA community at large (with the iCE40 and ECP5 receiving massive upticks in mindshare as a result).

What are some alternatives?

When comparing neorv32 and linux-on-litex-vexriscv you can also consider the following projects:

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip

picoMIPS - picoMIPS processor doing affine transformation

fpga-zynq - Support for Rocket Chip on Zynq FPGAs

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

butterstick-hardware - Basic ECP5 based GigE to SYZYGY interface.

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements

lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

nmigen-tutorial - A tutorial for using nmigen

litex - Build your hardware, easily!