simple-riscv
riscv-tests
| simple-riscv | riscv-tests | |
|---|---|---|
| 5 | 9 | |
| 19 | 790 | |
| - | 2.9% | |
| 2.7 | 7.5 | |
| about 3 years ago | about 1 hour ago | |
| VHDL | C | |
| MIT License | GNU General Public License v3.0 or later |
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simple-riscv
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How to run DOOM on a custom-made CPU in VHDL
Have a look at https://github.com/hamsternz/simple-riscv/tree/main/sw for how I did this for my toy processor. In particular https://github.com/hamsternz/simple-riscv/tree/main/sw/image_to_mem does the heavy lifting.
- Running VIVADO project from batch- linux , by using tcl file.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
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Is a single cycle CPU of any use besides learning?
If you want to see my ISA testing source have a look at: https://github.com/hamsternz/simple-riscv/blob/main/sw/asm/isa_test.S
riscv-tests
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Computerraria: A fully compliant RISC-V computer inside Terraria
Fully compliant to RISC-V how? Is it conforming to a specific RVI profile? The project states "By emulating a complete rv32i instruction set inside the wiring system of Terraria, we push back speeds to the early 70s era, tossing the ball firmly back into the court of silicon engineer without losing any software functionality."
So this is building a RISC-V *microcontroller* but what version of the ISA? 2.2 from 2017? Is it sucessfully passing conformance tests (https://github.com/riscv-software-src/riscv-tests)? I don't want to dunk on the project, but the title is over-selling and not scoping the context of the work. I look forward to some more updates from @misprit7!
Note: I'm the working group lead for distro-integration within the RISC-V Software Ecosystem (RISE) group.
- Verification
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
- Efficient Way To Generate Test Benches For MIPS Processor?
- We need some support
- Available (official) test suite?
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Compliance tests official repository
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
What are some alternatives?
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
riscv-arch-test
riscv-formal - RISC-V Formal Verification Framework
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
Cores-VeeR-EH1 - VeeR EH1 core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscof
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-compliance