riscv-tests
riscof
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| riscv-tests | riscof | |
|---|---|---|
| 9 | 2 | |
| 778 | 60 | |
| 3.9% | - | |
| 7.5 | 0.0 | |
| 13 days ago | 13 days ago | |
| C | Python | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-tests
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Computerraria: A fully compliant RISC-V computer inside Terraria
Fully compliant to RISC-V how? Is it conforming to a specific RVI profile? The project states "By emulating a complete rv32i instruction set inside the wiring system of Terraria, we push back speeds to the early 70s era, tossing the ball firmly back into the court of silicon engineer without losing any software functionality."
So this is building a RISC-V *microcontroller* but what version of the ISA? 2.2 from 2017? Is it sucessfully passing conformance tests (https://github.com/riscv-software-src/riscv-tests)? I don't want to dunk on the project, but the title is over-selling and not scoping the context of the work. I look forward to some more updates from @misprit7!
Note: I'm the working group lead for distro-integration within the RISC-V Software Ecosystem (RISE) group.
- Verification
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
- Efficient Way To Generate Test Benches For MIPS Processor?
- We need some support
- Available (official) test suite?
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Compliance tests official repository
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
riscof
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Senior Design Project Ideas?
Integration of the RISCOF test framework (https://github.com/riscv-software-src/riscof)
- Available (official) test suite?
What are some alternatives?
riscv-arch-test
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
riscv-code-size-reduction
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-compliance
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Artix-7-HDMI-processing - Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
riscv-formal - RISC-V Formal Verification Framework