Senior Design Project Ideas?

• minimax

  13 194 5.8 Verilog

  Minimax: a Compressed-First, Microcoded RISC-V CPU

  I develop Minimax (https://github.com/gsmecher/minimax), an open-source RISC-V implementation. It's currently written in both VHDL and Verilog (the two implementations are equivalent, though I am likely to drop the VHDL implementation if it's too much work to keep them both.)

• riscv-code-size-reduction

  9 150 6.0 Python

  

  Support for proposed Zc* instructions (https://github.com/riscv/riscv-code-size-reduction)

• InfluxDB

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• riscof

  2 60 1.1 Python

  

  Integration of the RISCOF test framework (https://github.com/riscv-software-src/riscof)

• Artix-7-HDMI-processing

  1 166 10.0 VHDL

  Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

  Using the Zybo’s HDMI in or out is way beyond a 14 week project unless you find a core that’s already done and base a project around that; see Mike Field (field hamster)‘s work on GitHub. https://github.com/hamsternz/Artix-7-HDMI-processing

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