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riscv-arch-test
The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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AppSignal
AppSignal knows why the f*#k it crashed. Stop vibe-debugging. Every exception, every backtrace, grouped so you see patterns, not noise.
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neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Here is a port for a custom RISC-V CPU: https://github.com/stnolting/neorv32/tree/master/sw/isa-test/port-neorv32
NOTE:
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Hence, a higher number means a more popular project.