How to verify Embench Benchmark in a RISC-V core?

This page summarizes the projects mentioned and recommended in the original post on reddit.com/r/RISCV

Our great sponsors
  • SonarLint - Clean code begins in your IDE with SonarLint
  • InfluxDB - Access the most powerful time series database as a service
  • SaaSHub - Software Alternatives and Reviews
  • neorv32

    🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    This highly depends on your RISC-V system. If you already have a UART you can use that to output data via printf (for example using newlib's system calls). But in most cases is pretty oversized as it requires 100s of kB of memory. I think it would be better to use some kind of "embedded printf" like this from the example provided above and just add the according "putc" function to send one char to your UART.

  • SonarLint

    Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

Suggest a related project

Related posts