Tips on building a RISC-V processor on FPGA

• VexRiscv

  21 2,244 7.6 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

• riscv-mini

  1 491 3.8 Scala

  Simple RISC-V 3-stage Pipeline in Chisel

  

• InfluxDB

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• riscv-tests

  9 771 7.8 C

  

  Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.

• dromajo

  1 198 6.0 C++

  RISC-V RV64GC emulator designed for RTL co-simulation

  

  Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.

• RISCV-FiveStage

  4 89 0.0 Scala

  Marginally better than redstone

• WorkOS

  workos.com

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