Riscv-formal Alternatives

Similar projects and alternatives to riscv-formal

VexRiscv

21 2,269 7.3 Assembly riscv-formal VS VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
lion

10 242 4.5 Haskell riscv-formal VS lion

Where Lions Roam: RISC-V on the VELDT (by standardsemiconductor)
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riscv-arch-test

8 462 8.5 Assembly riscv-formal VS riscv-arch-test
riscv-tests

9 790 7.5 C riscv-formal VS riscv-tests
riscv-isa-sim

15 2,211 9.0 C riscv-formal VS riscv-isa-sim

Spike, a RISC-V ISA Simulator
autofpga

9 157 4.3 C++ riscv-formal VS autofpga

A utility for Composing FPGA designs from Peripherals
Cores-VeeR-EH1

8 774 0.0 SystemVerilog riscv-formal VS Cores-VeeR-EH1

VeeR EH1 core
SaaSHub

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rp32

3 8 5.9 SystemVerilog riscv-formal VS rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
openarty

6 116 0.0 Verilog riscv-formal VS openarty

An Open Source configuration of the Arty platform
simple-riscv

5 19 2.7 VHDL riscv-formal VS simple-riscv

A simple three-stage RISC-V CPU
toolchain

4 - - riscv-formal VS toolchain
hs-arm

1 25 10.0 Haskell riscv-formal VS hs-arm

(Dis)assembler and analyzer generated from the machine-readable ARMv8.3-A specification
X86-64-semantics

1 130 10.0 Assembly riscv-formal VS X86-64-semantics

Semantics of x86-64 in K
planckRV32I

1 4 6.8 riscv-formal VS planckRV32I

Discontinued Core based on RV32I ISA
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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-formal alternative or higher similarity.

Suggest an alternative to riscv-formal

riscv-formal reviews and mentions

Posts with mentions or reviews of riscv-formal. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-12-10.

RISC-V simulator
3 projects | /r/RISCV | 10 Dec 2023

You might be able to hook up your simulator to risc v-formal https://github.com/SymbioticEDA/riscv-formal
how is to use symbiflow in my fpga projects.
1 project | /r/FPGA | 23 Mar 2022
Machine readable specifications at scale
3 projects | /r/ProgrammingLanguages | 30 Jan 2022

Then we have RISC, which wrote their own formal verification toolchain here. They just generate Verilog with a Python script. AFAICT this would be really hard to adapt to an assembler. Fortunately the ISA is simple to implement.
Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
4 projects | /r/RISCV | 23 Nov 2021
Is a single cycle CPU of any use besides learning?
4 projects | /r/RISCV | 31 Oct 2021
When to use Formal Verification vs Simulation?
1 project | /r/FPGA | 24 Jun 2021
Where Lions Roam: RISC-V on the VELDT
1 project | /r/RISCV | 28 Feb 2021

Your question is certainly not dumb; on the contrary, it is very important! I suppose the developers are responsible for verifying the formal verifier and ensuring it covers the spec. Maybe there is a way to formally verify the formal verifier? Either way, I must give a shout out to the riscv-formal project and its contributors; the project was instrumental to the development of Lion.

4 projects | /r/haskell | 28 Feb 2021

Not trying to put words in your mouth, but I do want to clarify something for this audience: the bound in the BMC done by the riscv-formal suite is on the number of cycles, not on the number of bits. Case in point, when you try to BMC the (M)ultiply extensions with the riscv-formal suite, you're actually not allowed to use multiplication because the state space blows up: https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md#alternative-arithmetic-operations
Any advices for my first RISC-V Core in Verilog ?
2 projects | /r/FPGA | 5 Feb 2021

Use riscv-formal. It will save a ton of headaches trying to track down a bad instruction. It can generate a module that does checks on the fly during normal sims.
FPGA and Simulation tools for Risc-V design
4 projects | /r/FPGA | 24 Dec 2020

I recommend SymbiYosys for formally testing your CPU before ever placing it into a simulation. You can use the riscv-formal property set to get you started, but I'd personally go for an inductive proof of some type and the riscv-formal property set may not get you that far.
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