A utility for Composing FPGA designs from Peripherals (by ZipCPU)

Autofpga Alternatives

Similar projects and alternatives to autofpga

  • GitHub repo VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

  • GitHub repo wb2axip

    Bus bridges and other odds and ends

  • GitHub repo sdspi

    SD-Card controller, using a SPI interface that is (optionally) shared

  • GitHub repo neorv32

    A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

  • GitHub repo riscv-formal

    RISC-V Formal Verification Framework

  • GitHub repo riscv-compliance

  • GitHub repo openarty

    An Open Source configuration of the Arty platform

  • GitHub repo nybbleForth

    Stack machine with 4-bit instructions

  • GitHub repo Rudi-RV32I

    A rudimental RISCV CPU supporting RV32I instructions, in VHDL

  • GitHub repo dbgbus

    A collection of debugging busses developed and presented at

  • GitHub repo icozip

    A ZipCPU demonstration port for the icoboard

NOTE: The number of mentions on this list indicates mentions on common posts. Hence, a higher number means a better autofpga alternative or higher similarity.


Posts where autofpga has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-07-22.
  • SoC FPGA design to ASIC | 2021-07-22
    An SoC composer? You'll need something that takes multiple bus components and stitches them together. I've used AutoFPGA extensively for this purpose, and continue to do so today. It's biggest problem? I haven't put a lot of energy into marketing it, so the documentation is more lacking than I would like. Still, it's worked quite well for me and my intermediate tutorial (work in progress) provides some discussion of how to work with it.
  • Tricks to make AXI wiring faster in Verilog | 2021-07-15
    AutoFPGA can do simple bus line pattern substitution. For example, these two configuration lines then expand to these 65 lines.
  • CPU DESIGN | 2021-04-05
    There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
  • Auto generate header files | 2021-01-16
    I generated my own solution to this problem, a solution which I called AutoFPGA. It's not IP-XACT. It configures a design based upon a bus with (potentially) multiple masters and slaves. Configuration files are designed on a per-unit basis, with the intention that a slave (or master) configuration file could be removed to remove that portion of the design from the whole.
  • FPGA and Simulation tools for Risc-V design | 2020-12-24
    If you wish to build a SOC design, you'll need some approach to assembling the bus together. There will be a lot of wires to connect, and a lot of logic to build just to get you off the ground. You'll find several SOC based building tools out there to use. I've built my own, AutoFPGA, which I use for assembling peripherals around a CPU based design. You might find an open source crossbar interconnect to be quite valuable as well. I've built crossbars for AXI, AXI-lite, and Wishbone (pipeline). I know there's a good Wishbone classic crossbar out there as well, I just don't have the link at my fingertips. (Good? It'll slow down your overall clock speed, while yielding poorer performance compared to Wishbone pipeline--but that's just the reality of working with Wishbone classic.)


Basic autofpga repo stats
about 1 month ago

ZipCPU/autofpga is an open source project licensed under GNU General Public License v3.0 only which is an OSI approved license.