Autofpga Alternatives

autofpga reviews and mentions

• How do you wire modules together?
  1 project | /r/FPGA | 19 Mar 2023

  I use AutoFPGA for connecting my top level components together. It handles bus composition and address assignment for me, while also creating linker, C header and Verilator simulation files for the project. Once a project is set up, reconfiguration is as easy as adding a file to the command line to add a component, or removing a file from the command line to remove a component. Make handles the rest.

• Tricks to make AXI wiring faster in Verilog?
  1 project | /r/FPGA | 15 Jul 2022

  I use AutoFPGA for all my bus connections. A single @$(SLAVE.PORTLIST) or @$(SLAVE.ANSPORTLIST) automatically expands into the connections required when instantiating a module. It'll also instantiate the crossbar for you as well.

• AXI InterConnect
  3 projects | /r/FPGA | 28 Jun 2022

  Yes, I have posted an open source AXI interconnect. Unlike Xilinx's interconnect, mine doesn't automatically bridge between one bus width or clock and another, although some bridges exist in the same repository. Bridges exist, for example, for crossing clock domains, going from AXI3 to AXI4, from AXI4 to AXI4-lite, from AXI4 to a smaller AXI4-lite, and from AXI4-lite to a wider width. It's been enough to keep me from needing my own AXI4 interconnect, although AXI can be a real pain to wire up. As a result, I tend to use AutoFPGA for that purpose.

• Hey Xilinx users, let me have it...
  4 projects | /r/FPGA | 13 Aug 2021

  Now, whether or not AutoFPGA fits the bill for anyone--that's an entirely different question. I suspect the answer is, "No", but that's really a different conversation for a different time/thread. One of the things it can do is compose an AXI bus from multiple master and slave configurations--all using user controlled and very version controllable configuration files. The big problem it has (currently) is the lack of a strong verification suite. That's probably going to hit the top of my to-do list soon enough.

• SoC FPGA design to ASIC
  4 projects | /r/FPGA | 22 Jul 2021

  An SoC composer? You'll need something that takes multiple bus components and stitches them together. I've used AutoFPGA extensively for this purpose, and continue to do so today. It's biggest problem? I haven't put a lot of energy into marketing it, so the documentation is more lacking than I would like. Still, it's worked quite well for me and my intermediate tutorial (work in progress) provides some discussion of how to work with it.

• Tricks to make AXI wiring faster in Verilog
  1 project | /r/FPGA | 15 Jul 2021

  AutoFPGA can do simple bus line pattern substitution. For example, these two configuration lines then expand to these 65 lines.

• CPU DESIGN
  9 projects | /r/FPGA | 5 Apr 2021

  There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.

• Auto generate header files
  1 project | /r/FPGA | 16 Jan 2021

  I generated my own solution to this problem, a solution which I called AutoFPGA. It's not IP-XACT. It configures a design based upon a bus with (potentially) multiple masters and slaves. Configuration files are designed on a per-unit basis, with the intention that a slave (or master) configuration file could be removed to remove that portion of the design from the whole.

• FPGA and Simulation tools for Risc-V design
  4 projects | /r/FPGA | 24 Dec 2020

  If you wish to build a SOC design, you'll need some approach to assembling the bus together. There will be a lot of wires to connect, and a lot of logic to build just to get you off the ground. You'll find several SOC based building tools out there to use. I've built my own, AutoFPGA, which I use for assembling peripherals around a CPU based design. You might find an open source crossbar interconnect to be quite valuable as well. I've built crossbars for AXI, AXI-lite, and Wishbone (pipeline). I know there's a good Wishbone classic crossbar out there as well, I just don't have the link at my fingertips. (Good? It'll slow down your overall clock speed, while yielding poorer performance compared to Wishbone pipeline--but that's just the reality of working with Wishbone classic.)

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