openarty

An Open Source configuration of the Arty platform (by ZipCPU)

Openarty Alternatives

Similar projects and alternatives to openarty

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better openarty alternative or higher similarity.

openarty reviews and mentions

Posts with mentions or reviews of openarty. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-11.
  • C++ Verification Testbench Best-Practice Resources?
    7 projects | /r/FPGA | 11 Jun 2023
    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
  • PPS detection/regeneration
    2 projects | /r/FPGA | 25 May 2022
    Feel free to check out my own implementation of this requirement. It essentially connects a tracking loop to the difference between the locally regenerated PPS and the incoming PPS signal. With the right control inputs, I was able to drive the loop error below 1us or so.
    2 projects | /r/FPGA | 25 May 2022
    The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
  • FPGA and Simulation tools for Risc-V design
    4 projects | /r/FPGA | 24 Dec 2020
    I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).
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    www.influxdata.com | 3 Mar 2024
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over 3 years ago
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