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Sdspi Alternatives
Similar projects and alternatives to sdspi
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neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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InfluxDB
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SaaSHub
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FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
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SaaSHub
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better sdspi alternative or higher similarity.
sdspi discussion
sdspi reviews and mentions
Posts with mentions or reviews of sdspi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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Envisioning the Ultimate I2C Controller
You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?
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SoC FPGA design to ASIC
How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.
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CPU DESIGN
There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
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Stats
Basic sdspi repo stats
4
278
8.5
20 days ago
The primary programming language of sdspi is Verilog.
Sponsored
InfluxDB – Built for High-Performance Time Series Workloads
InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.
www.influxdata.com