A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (by ZipCPU)

Zbasic Alternatives

Similar projects and alternatives to zbasic based on common topics and language

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better zbasic alternative or higher similarity.

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Reviews and mentions

Posts with mentions or reviews of zbasic. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-07-07.
  • How do you successfully compile a working verilator package on Ubuntu?
    reddit.com/r/ZipCPU | 2021-07-27
    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
  • Need help with Objcopy for Verilog Hex File
    reddit.com/r/FPGA | 2021-07-07
    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
  • How can I get Verilator to Prompt for User Input?
    reddit.com/r/FPGA | 2021-04-19
    The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.


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