Zbasic Alternatives

Similar projects and alternatives to zbasic

openarty

6 116 0.0 Verilog zbasic VS openarty

An Open Source configuration of the Arty platform
qspiflash

4 63 0.0 Verilog zbasic VS qspiflash

A set of Wishbone Controlled SPI Flash Controllers
InfluxDB

www.influxdata.com sponsored

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openlane

12 1,174 8.6 Python zbasic VS openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
dbgbus

5 31 3.9 Verilog zbasic VS dbgbus

A collection of debugging busses developed and presented at zipcpu.com
wbuart32

4 246 4.6 Verilog zbasic VS wbuart32

A simple, basic, formally verified UART controller
arrowzip

3 19 0.0 Verilog zbasic VS arrowzip

A ZipCPU based demonstration of the MAX1000 FPGA board
fpga_quick_ram_update

1 13 1.8 Verilog zbasic VS fpga_quick_ram_update

Quickly update a bitstream with new RAM contents
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
dpll

2 87 2.8 Verilog zbasic VS dpll

A collection of phase locked loop (PLL) related projects

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better zbasic alternative or higher similarity.

Suggest an alternative to zbasic

zbasic reviews and mentions

Posts with mentions or reviews of zbasic. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-01-10.

AXI Quad SPI 3.2 Flash programming scripts
5 projects | /r/FPGA | 10 Jan 2022

Here's sort of a generic repo you can look at which might give you some ideas.
How do you successfully compile a working verilator package on Ubuntu?
1 project | /r/ZipCPU | 27 Jul 2021

Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
Need help with Objcopy for Verilog Hex File
3 projects | /r/FPGA | 7 Jul 2021

As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
How can I get Verilator to Prompt for User Input?
3 projects | /r/FPGA | 19 Apr 2021

The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.
A note from our sponsor - InfluxDB
www.influxdata.com | 19 Apr 2024

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