openarty
An Open Source configuration of the Arty platform (by ZipCPU)
riscv-arch-test
By riscv-non-isa
| openarty | riscv-arch-test | |
|---|---|---|
| 6 | 8 | |
| 116 | 462 | |
| - | 1.9% | |
| 0.0 | 8.5 | |
| 4 months ago | 2 days ago | |
| Verilog | Assembly | |
| - | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
openarty
Posts with mentions or reviews of openarty.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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PPS detection/regeneration
The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
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AXI Quad SPI 3.2 Flash programming scripts
Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
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Arty S7 - 2 different flash brands
You can compare my configuration file for the Spansion flash with my config file for the Micron flash to see that these are the only two hardware differences between the two
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FPGA and Simulation tools for Risc-V design
I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).
riscv-arch-test
Posts with mentions or reviews of riscv-arch-test.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
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Heed help with riscv-arch-test
git: https://github.com/riscv-non-isa/riscv-arch-test.git commit: 6d87f30 (current master)
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Available (official) test suite?
There's also https://github.com/riscv-non-isa/riscv-arch-test, which I think is using similar tests to riscof (some generated by riscv_ctg) just an older framework to run it all.
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Problems with riscv-arch-test
Prior notice, I work for a professor and he wants me to test/verify a riscv simulation model, which is programmed in VHDL. He referred to the https://github.com/riscv-non-isa/riscv-arch-test , to look up how I have to set up a test.
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Compliance tests official repository
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
Have you tried running the RISC-V architectural test suite: https://github.com/riscv/riscv-arch-test? It should fit pretty nicely with your test system, each test generates a signature that needs to be checked against an expected output.
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FPGA and Simulation tools for Risc-V design
There are official RISC V tests you can run: https://github.com/riscv/riscv-compliance
What are some alternatives?
When comparing openarty and riscv-arch-test you can also consider the following projects:
zipcpu - A small, light weight, RISC CPU soft core
riscv-tests
wbicapetwo - Wishbone to ICAPE interface conversion
riscv-formal - RISC-V Formal Verification Framework
qspiflash - A set of Wishbone Controlled SPI Flash Controllers
riscv-isa-sim - Spike, a RISC-V ISA Simulator
autofpga - A utility for Composing FPGA designs from Peripherals
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rrs - Rust RISC-V Simulator
wbuart32 - A simple, basic, formally verified UART controller
riscof
openarty vs zipcpu
riscv-arch-test vs riscv-tests
openarty vs wbicapetwo
riscv-arch-test vs riscv-formal
openarty vs qspiflash
riscv-arch-test vs riscv-isa-sim
openarty vs autofpga
riscv-arch-test vs neorv32
openarty vs riscv-formal
riscv-arch-test vs rrs
openarty vs wbuart32
riscv-arch-test vs riscof