riscv-arch-test
By riscv-non-isa
riscof
By riscv-software-src
Our great sponsors
| riscv-arch-test | riscof | |
|---|---|---|
| 8 | 2 | |
| 463 | 60 | |
| 3.7% | - | |
| 8.1 | 0.0 | |
| 10 days ago | 11 days ago | |
| Assembly | Python | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-arch-test
Posts with mentions or reviews of riscv-arch-test.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
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Heed help with riscv-arch-test
git: https://github.com/riscv-non-isa/riscv-arch-test.git commit: 6d87f30 (current master)
-
Available (official) test suite?
There's also https://github.com/riscv-non-isa/riscv-arch-test, which I think is using similar tests to riscof (some generated by riscv_ctg) just an older framework to run it all.
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Problems with riscv-arch-test
Prior notice, I work for a professor and he wants me to test/verify a riscv simulation model, which is programmed in VHDL. He referred to the https://github.com/riscv-non-isa/riscv-arch-test , to look up how I have to set up a test.
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Compliance tests official repository
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
Have you tried running the RISC-V architectural test suite: https://github.com/riscv/riscv-arch-test? It should fit pretty nicely with your test system, each test generates a signature that needs to be checked against an expected output.
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FPGA and Simulation tools for Risc-V design
There are official RISC V tests you can run: https://github.com/riscv/riscv-compliance
riscof
Posts with mentions or reviews of riscof.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-21.
-
Senior Design Project Ideas?
Integration of the RISCOF test framework (https://github.com/riscv-software-src/riscof)
- Available (official) test suite?
What are some alternatives?
When comparing riscv-arch-test and riscof you can also consider the following projects:
riscv-tests
riscv-formal - RISC-V Formal Verification Framework
riscv-code-size-reduction
riscv-isa-sim - Spike, a RISC-V ISA Simulator
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
rrs - Rust RISC-V Simulator
riscv-compliance
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Artix-7-HDMI-processing - Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
openarty - An Open Source configuration of the Arty platform
riscv-arch-test vs riscv-tests
riscof vs riscv-tests
riscv-arch-test vs riscv-formal
riscof vs riscv-code-size-reduction
riscv-arch-test vs riscv-isa-sim
riscof vs minimax
riscv-arch-test vs rrs
riscof vs riscv-compliance
riscv-arch-test vs neorv32
riscof vs Artix-7-HDMI-processing
riscv-arch-test vs openarty
riscv-arch-test vs riscv-compliance