riscv-arch-test
By riscv-non-isa
rrs
Rust RISC-V Simulator (by GregAC)
Our great sponsors
| riscv-arch-test | rrs | |
|---|---|---|
| 8 | 2 | |
| 463 | 21 | |
| 3.7% | - | |
| 8.1 | 3.0 | |
| 10 days ago | 10 months ago | |
| Assembly | Rust | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-arch-test
Posts with mentions or reviews of riscv-arch-test.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
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Heed help with riscv-arch-test
git: https://github.com/riscv-non-isa/riscv-arch-test.git commit: 6d87f30 (current master)
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Available (official) test suite?
There's also https://github.com/riscv-non-isa/riscv-arch-test, which I think is using similar tests to riscof (some generated by riscv_ctg) just an older framework to run it all.
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Problems with riscv-arch-test
Prior notice, I work for a professor and he wants me to test/verify a riscv simulation model, which is programmed in VHDL. He referred to the https://github.com/riscv-non-isa/riscv-arch-test , to look up how I have to set up a test.
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Compliance tests official repository
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
Have you tried running the RISC-V architectural test suite: https://github.com/riscv/riscv-arch-test? It should fit pretty nicely with your test system, each test generates a signature that needs to be checked against an expected output.
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FPGA and Simulation tools for Risc-V design
There are official RISC V tests you can run: https://github.com/riscv/riscv-compliance
rrs
Posts with mentions or reviews of rrs.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-23.
-
What's everyone working on this week (34/2021)?
I'm implementing more of a RISC-V instruction set simulator I started a while ago: https://github.com/GregAC/rrs
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
I've been working on something along very similar lines https://github.com/GregAC/rrs (I should look into getting it on crates.io) had been planning a test system similar to yours though have yet to implement it.
What are some alternatives?
When comparing riscv-arch-test and rrs you can also consider the following projects:
riscv-tests
xv6-riscv - Xv6 for RISC-V
riscv-formal - RISC-V Formal Verification Framework
lambda-calculus - A lambda calculus interpreter that works on desktop and wasm
riscv-isa-sim - Spike, a RISC-V ISA Simulator
crates.io - The Rust package registry
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
lib-rv32 - Rust library for emulating RISC-V rv32imac
riscof
yarve - RISC-V emulator in Rust
openarty - An Open Source configuration of the Arty platform
uom - Units of measurement -- type-safe zero-cost dimensional analysis