Vgasim Alternatives

vgasim reviews and mentions

• C++ Verification Testbench Best-Practice Resources?
  7 projects | /r/FPGA | 11 Jun 2023

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• Sobel algorithm in VHDL help
  2 projects | /r/FPGA | 17 May 2022

  Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.

• Any good tips for writing IP that inputs/outputs AXI stream?
  2 projects | /r/FPGA | 6 Mar 2022

  Definitely. To see how this might build up, consider this video sprite module. At each stage, counting from the end, the READY backs up.

• Simulate FPGA with other ICs
  2 projects | /r/FPGA | 29 Nov 2021

  Ahm ... I've certainly added C components to my test bench to create and simulate graphical interfaces. Here's one for VGA, and another for HDMI. This isn't really a "nobody does this" task. It's much easier to debug a graphical component graphically than it is to debug it with a wave file. Indeed, I owe my success in one particular video decompression example to being able to stop the simulation in real time in order to find and trace a bug.

• More thorough resources for Verilator
  1 project | /r/FPGA | 14 Jul 2021

  Yes--I've done that with both VGA and HDMI. You can find the example here if you want to see how I did it.

• How does one verify audio- and video signal processing designs?
  1 project | /r/FPGA | 6 Jul 2021

  Check out this page describing these techniques, or even the repository containing my simulator.

• It's been three days and I couldn't find the problem. Any help is appreciated.
  1 project | /r/FPGA | 4 Feb 2021

  Why not try a Verilator based simulation like this one? You'd then be able to see the (broken) design on a window of your simulation host's screen, and capture a VCD file to see what's going on (or not)? You should be able to just place the VGA outputs into the VGASIM class to be able to see the image on your screen. Multiple video modes are supported, so select the one you need. (The demo works with all modes, but the memory mapped frame buffer's image is only built for 1280x1024, and hence the requirement in the demo).

• Is there a standard way of programming (Verilog) to use things that happen two or three clock cycles in the future?
  1 project | /r/FPGA | 1 Feb 2021

  For an example, you might wish to take a look at the histogram design I posted. Other valuable examples might include the slow filter, the slow linear phase filter, the downsampler, or even the FFT Window function. I've also got a sprite video design that I'd like to write about, but haven't had the chance to test yet. All of these designs need to deal with and work around these issues with internal block RAM.

• Need help with HDL testbench
  1 project | /r/FPGA | 25 Jan 2021

  I have a variety of C++ simulation sources that I use which can create either VGA or HDMI signals to input into a test bench--together with a couple example designs that demonstrate these test benches. They work nicely with Verilator.

• Getting DDR3 working on Arty-Z10
  4 projects | /r/FPGA | 1 Jan 2021

  This demo shows how the AXI stream framed data can be turned to pixels and sent to a screen--should that be your wish.

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