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Verilog-pcie Alternatives
Similar projects and alternatives to verilog-pcie
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verilog-pcie reviews and mentions
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
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A note from our sponsor - SaaSHub
www.saashub.com | 26 Apr 2024
Stats
alexforencich/verilog-pcie is an open source project licensed under MIT License which is an OSI approved license.
The primary programming language of verilog-pcie is Verilog.
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