verilog-pcie VS dma_ip_drivers

The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.

Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.

For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.

Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh

You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.

I don't have experience with XDMA and PCI Express IP either, but from the block diagram, I can see that it is controlled either via CFG AXI or an internal "bridge" interface which can be accessed directly by the PCI subsystem. So, I would expect you should be able to use a driver like this to set up your memcpy transfers.

the latest release is here https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel

This subject will get its own post in the near future. The Host operating system is Arch Linux. The Host processor loads the FPGA image, receives samples over PCIe, controls power supplies, configures the ADCs, orchestrates the RF frontend, and serves up an RPC interface. Host software is a combination of C++ and Python. The signal path is entirely C++. Python is for management and frontend control. I’m using the Xilinx PCIe DMA kernel module (XDMA) to stream samples and access FPGA control registers from userspace.

You can generate an example project for PCIe in Vivado. If you create an instance of XDMA in your project and right-click in the IP Integrator there should be an option to generate the example project. You can then use [this project](https://github.com/Xilinx/dma_ip_drivers) to profile the data transfer rate across the link.