verilog-pcie
Verilog PCI express components (by alexforencich)
vgasim
A Video display simulator (by ZipCPU)
verilog-pcie | vgasim | |
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8 | 11 | |
951 | 147 | |
- | - | |
6.5 | 1.2 | |
11 days ago | about 1 year ago | |
Verilog | Verilog | |
MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-pcie
Posts with mentions or reviews of verilog-pcie.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
vgasim
Posts with mentions or reviews of vgasim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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Sobel algorithm in VHDL help
Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.
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Any good tips for writing IP that inputs/outputs AXI stream?
Definitely. To see how this might build up, consider this video sprite module. At each stage, counting from the end, the READY backs up.
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Simulate FPGA with other ICs
Ahm ... I've certainly added C components to my test bench to create and simulate graphical interfaces. Here's one for VGA, and another for HDMI. This isn't really a "nobody does this" task. It's much easier to debug a graphical component graphically than it is to debug it with a wave file. Indeed, I owe my success in one particular video decompression example to being able to stop the simulation in real time in order to find and trace a bug.
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More thorough resources for Verilator
Yes--I've done that with both VGA and HDMI. You can find the example here if you want to see how I did it.
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How does one verify audio- and video signal processing designs?
Check out this page describing these techniques, or even the repository containing my simulator.
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It's been three days and I couldn't find the problem. Any help is appreciated.
Why not try a Verilator based simulation like this one? You'd then be able to see the (broken) design on a window of your simulation host's screen, and capture a VCD file to see what's going on (or not)? You should be able to just place the VGA outputs into the VGASIM class to be able to see the image on your screen. Multiple video modes are supported, so select the one you need. (The demo works with all modes, but the memory mapped frame buffer's image is only built for 1280x1024, and hence the requirement in the demo).
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Is there a standard way of programming (Verilog) to use things that happen two or three clock cycles in the future?
For an example, you might wish to take a look at the histogram design I posted. Other valuable examples might include the slow filter, the slow linear phase filter, the downsampler, or even the FFT Window function. I've also got a sprite video design that I'd like to write about, but haven't had the chance to test yet. All of these designs need to deal with and work around these issues with internal block RAM.
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Need help with HDL testbench
I have a variety of C++ simulation sources that I use which can create either VGA or HDMI signals to input into a test bench--together with a couple example designs that demonstrate these test benches. They work nicely with Verilator.
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Getting DDR3 working on Arty-Z10
This demo shows how the AXI stream framed data can be turned to pixels and sent to a screen--should that be your wish.
What are some alternatives?
When comparing verilog-pcie and vgasim you can also consider the following projects:
dma_ip_drivers - Xilinx QDMA IP Drivers
biriscv - 32-bit Superscalar RISC-V CPU
nitefury-popr
wb2axip - Bus bridges and other odds and ends
riscv - RISC-V CPU Core (RV32IM)
dpll - A collection of phase locked loop (PLL) related projects
fftdemo - A demonstration showing how several components can be compsed to build a simulated spectrogram
FakePGA - Simulating Verilog designs on a microcontroller
videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality
dspfilters - A collection of demonstration digital filters
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
COLOR_PAL - 512 / 64 Colors Composite PAL modulator using Verilog