Dma_ip_drivers Alternatives

dma_ip_drivers reviews and mentions

• xdma : understanding how dma_streaming_test script sets streaming mode
  1 project | /r/FPGA | 14 Oct 2023
• Does Xilinx's XDMA automaticly copy data from PCIe to DDR4 and from DDR4 to PCIe base on PCIe command?
  1 project | /r/FPGA | 10 Mar 2022

  I don't have experience with XDMA and PCI Express IP either, but from the block diagram, I can see that it is controlled either via CFG AXI or an internal "bridge" interface which can be accessed directly by the PCI subsystem. So, I would expect you should be able to use a driver like this to set up your memcpy transfers.

• Use a xilinx pcie board as an accelerator
  1 project | /r/FPGA | 25 Jan 2022

  the latest release is here https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel

• Wideband SDR Platform on a Budget, Update # 2, Observations of Starlink Downlink w/ Software Defined Radio
  1 project | /r/RTLSDR | 16 Jan 2022

  This subject will get its own post in the near future. The Host operating system is Arch Linux. The Host processor loads the FPGA image, receives samples over PCIe, controls power supplies, configures the ADCs, orchestrates the RF frontend, and serves up an RPC interface. Host software is a combination of C++ and Python. The signal path is entirely C++. Python is for management and frontend control. I’m using the Xilinx PCIe DMA kernel module (XDMA) to stream samples and access FPGA control registers from userspace.

• PCIe Express on Artix-7 Board?
  3 projects | /r/FPGA | 17 Jan 2021

  You can generate an example project for PCIe in Vivado. If you create an instance of XDMA in your project and right-click in the IP Integrator there should be an option to generate the example project. You can then use [this project](https://github.com/Xilinx/dma_ip_drivers) to profile the data transfer rate across the link.

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