verilog-pcie
Verilog PCI express components (by alexforencich)
Sentinel-65X
A cost-reduced 65816-compatible retrocomputer (by studio8502)
| verilog-pcie | Sentinel-65X | |
|---|---|---|
| 8 | 1 | |
| 951 | 9 | |
| - | - | |
| 6.5 | 7.4 | |
| 11 days ago | about 2 months ago | |
| Verilog | C | |
| MIT License | CERN Open Hardware Licence Version 2 - Permissive |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-pcie
Posts with mentions or reviews of verilog-pcie.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
Sentinel-65X
Posts with mentions or reviews of Sentinel-65X.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
-
FuryGpu – Custom PCIe FPGA GPU
You might find the Sentinel 65X interesting in that the guy behind it basically said "the X16 is big and clunky and expensive, let's cut out that stuff".
https://github.com/studio8502/Sentinel-65X
It's not yet a deliverable product but watching the developers work on it has been an entertaining part of my doomscrolling diet.
What are some alternatives?
When comparing verilog-pcie and Sentinel-65X you can also consider the following projects:
dma_ip_drivers - Xilinx QDMA IP Drivers
nitefury-popr
vgasim - A Video display simulator