verilog-pcie
Verilog PCI express components (by alexforencich)
dma_ip_drivers
Xilinx QDMA IP Drivers (by Xilinx)
verilog-pcie | dma_ip_drivers | |
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8 | 5 | |
951 | 498 | |
- | 2.6% | |
6.5 | 5.0 | |
11 days ago | 6 days ago | |
Verilog | C | |
MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-pcie
Posts with mentions or reviews of verilog-pcie.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
dma_ip_drivers
Posts with mentions or reviews of dma_ip_drivers.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-01-17.
- xdma : understanding how dma_streaming_test script sets streaming mode
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Does Xilinx's XDMA automaticly copy data from PCIe to DDR4 and from DDR4 to PCIe base on PCIe command?
I don't have experience with XDMA and PCI Express IP either, but from the block diagram, I can see that it is controlled either via CFG AXI or an internal "bridge" interface which can be accessed directly by the PCI subsystem. So, I would expect you should be able to use a driver like this to set up your memcpy transfers.
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Use a xilinx pcie board as an accelerator
the latest release is here https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel
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Wideband SDR Platform on a Budget, Update # 2, Observations of Starlink Downlink w/ Software Defined Radio
This subject will get its own post in the near future. The Host operating system is Arch Linux. The Host processor loads the FPGA image, receives samples over PCIe, controls power supplies, configures the ADCs, orchestrates the RF frontend, and serves up an RPC interface. Host software is a combination of C++ and Python. The signal path is entirely C++. Python is for management and frontend control. I’m using the Xilinx PCIe DMA kernel module (XDMA) to stream samples and access FPGA control registers from userspace.
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PCIe Express on Artix-7 Board?
You can generate an example project for PCIe in Vivado. If you create an instance of XDMA in your project and right-click in the IP Integrator there should be an option to generate the example project. You can then use [this project](https://github.com/Xilinx/dma_ip_drivers) to profile the data transfer rate across the link.
What are some alternatives?
When comparing verilog-pcie and dma_ip_drivers you can also consider the following projects:
nitefury-popr
vgasim - A Video display simulator