verilog-pcie
Verilog PCI express components (by alexforencich)
FPGA_DisplayPort
An implementation of DisplayPort protocol for FPGAs (by hamsternz)
verilog-pcie | FPGA_DisplayPort | |
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8 | 3 | |
951 | 274 | |
- | - | |
6.5 | 10.0 | |
10 days ago | almost 8 years ago | |
Verilog | VHDL | |
MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-pcie
Posts with mentions or reviews of verilog-pcie.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
FPGA_DisplayPort
Posts with mentions or reviews of FPGA_DisplayPort.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
-
FuryGpu – Custom PCIe FPGA GPU
There is an open-source DisplayPort transmitter [1] that apparently supports multiple 2.7 Gbps lanes (albeit using family-specific SERDES/differential transceiver blocks, but I doubt that's avoidable at these speeds). This isn't PCIe, but it's also surprisingly close to PCIe 1.0 (2.5 Gbps/lane, and IIRC they use the same 8b/10b code and scrambling algorithm).
[1] https://github.com/hamsternz/FPGA_DisplayPort
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Thunderbolt 4 display converter — 1x 4-lane HBR2/DSC in, 2x 4-lane HBR2 out…dumb hobby project, what do you think?
I have quite a bit of experience working with DisplayPort on both FPGAs and ASICs, and I can tell you this: creating a very basic DisplayPort RX or TX in Verilog is an advanced project. There is some IP (see here), but that doesn't come close to covering your needs.
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FPGA for graphics processing?
It depends on what kind of processing but there's some basic hdmi and display port input and decoding examples https://github.com/hamsternz/FPGA_DisplayPort
What are some alternatives?
When comparing verilog-pcie and FPGA_DisplayPort you can also consider the following projects:
dma_ip_drivers - Xilinx QDMA IP Drivers
gplgpu - GPL v3 2D/3D graphics engine in verilog
nitefury-popr
vgasim - A Video display simulator