A ZipCPU based demonstration of the MAX1000 FPGA board (by ZipCPU)

Arrowzip Alternatives

Similar projects and alternatives to arrowzip

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arrowzip reviews and mentions

Posts with mentions or reviews of arrowzip. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-11.
  • C++ Verification Testbench Best-Practice Resources?
    7 projects | /r/FPGA | 11 Jun 2023
    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
  • SDR SDRAM Controller in Verilog (MT48LC16M16)
    2 projects | /r/FPGA | 1 Feb 2021
    If it would help, here are two SDRAM controllers: The first is for a winbond W9825G6JH (4M x 4 banks x 16 bits). It was designed for the XuLA-LX25 FPGA board, although it also works on my MAX-1000 board from Arrow as well. Beware, the clock needs to be offset 90 degrees from the data. The second controller works on an ISSI IS42S16100H/IS45S16100H SDRAM. Both use Wishbone (pipeline) interfaces. If you aren't using Wishbone, you might need a converter to ... whatever bus protocol you are using.
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