Dbgbus Alternatives

dbgbus reviews and mentions

• AXI Quad SPI 3.2 Flash programming scripts
  5 projects | /r/FPGA | 10 Jan 2022

  I've got a couple different encodings I use to push data over the serial port. Here's the hexbus encoding for example, although I more often use the WBUBUS encoding which you can find attached to many of my projects. They're all based around what I call a "debugging bus" and a "devbus interface". It's really easy to use--once you have it set up.

• Need help with Objcopy for Verilog Hex File
  3 projects | /r/FPGA | 7 Jul 2021

  As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.

• How can I get Verilator to Prompt for User Input?
  3 projects | /r/FPGA | 19 Apr 2021

  The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.

• CPU DESIGN
  9 projects | /r/FPGA | 5 Apr 2021

  There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.

• Bidirectional AXI data channel
  2 projects | /r/FPGA | 27 Jan 2021

  My personal solution to this problem has been to convert bus commands to UART commands. In my world, however, the PC/host sets up the UART commands and the FPGA decodes them into bus commands and then encodes a return value. This is useful because it can be done in 2 wires. I've also done it for JTAG (similar to SPI as implemented) where it takes 4 wires. Check out my articles on the "debugging bus" if you'd like to read more about this approach. (I now have AXI drivers for my debugging bus as well.)

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